Understanding the Rockchip MIPI DSI Controller Capabilities
Rockchip SoCs vary in their MIPI DSI controller specifications. The RK3288 has a single MIPI DSI controller that supports up to 4 data lanes, with a maximum clock frequency of 1.0 GHz, which translates to a per-lane data rate of 1.0 Gbps in D-PHY mode. The RK3399 has two MIPI DSI controllers, but for a single display you typically use one, and it supports up to 4 lanes with a maximum clock of 1.5 GHz, giving you 1.5 Gbps per lane. The RK3566 and RK3588 are newer, with the RK3588 supporting up to 4 lanes at 2.5 Gbps per lane, but the HDMI-to-MIPI bridge chip must match these speeds. The LT8911B, for instance, has a maximum MIPI DSI clock of 1.5 GHz, so it pairs well with the RK3399 but may bottleneck the RK3588 at higher resolutions. For 4K@30Hz, you need at least 8.9 Gbps of bandwidth, which requires 4 lanes at 2.2 Gbps each—something the LT8911B cannot handle. In that case, you would need an Lontium LT8912B or Analogix ANX7580, which support 4 lanes at 2.5 Gbps. The table below shows the key parameters for common Rockchip SoCs and bridge chips:
| SoC / Bridge Chip | Max MIPI Clock (MHz) | Max Per-Lane Data Rate (Gbps) | Max Resolution (4 lanes) | HDMI Version |
|---|---|---|---|---|
| RK3288 | 1000 | 1.0 | 1920x1080@60Hz | N/A (HDMI out only) |
| RK3399 | 1500 | 1.5 | 1920x1080@60Hz | N/A |
| RK3566 | 1500 | 1.5 | 1920x1080@60Hz | N/A |
| RK3588 | 2500 | 2.5 | 3840x2160@30Hz | N/A |
| LT8911B | 1500 | 1.5 | 1920x1080@60Hz | 1.4 |
| LT8912B | 2500 | 2.5 | 3840x2160@30Hz | 2.0 |
When you use an HDMI-to-MIPI adapter, the bridge chip emulates an EDID to the HDMI source, typically reporting a 1920x1080@60Hz capability. The Rockchip board then reads the MIPI DSI panel’s timing parameters from the device tree or a fixed configuration. The key is to ensure the MIPI DSI clock frequency matches the pixel clock of the HDMI input. For 1080p@60Hz, the pixel clock is 148.5 MHz, and with 4 lanes, the MIPI clock is roughly 148.5 MHz / 4 = 37.125 MHz, but you also need to account for blanking intervals and data overhead. In practice, the MIPI clock is set to around 500 MHz to 1.0 GHz depending on the bridge chip’s internal PLL. The LT8911B uses a PLL to multiply the HDMI pixel clock to a higher MIPI clock, typically 4x or 8x, to achieve the required data rate. For example, at 1080p@60Hz, the LT8911B outputs MIPI DSI at 1.0 Gbps per lane, which is well within its 1.5 Gbps limit.
Hardware Wiring and Signal Integrity Considerations
The physical connection between the HDMI-to-MIPI adapter and the Rockchip board requires careful attention to signal integrity. The MIPI DSI interface uses differential pairs for each data lane and the clock lane. The four data lanes are labeled D0+, D0-, D1+, D1-, D2+, D2-, D3+, D3-, and the clock lane is CLK+, CLK-. The Rockchip board typically exposes these on a 40-pin or 30-pin FPC connector, such as the common 0.5mm pitch 30-pin connector used on the RK3399 Firefly or RK3566 Orange Pi. The adapter board usually has a similar connector. The trace length between the adapter and the Rockchip board should be kept under 10 cm to avoid signal degradation, and the impedance must be 100 ohms differential for the MIPI lanes. If you use a longer cable, you risk clock jitter and data errors, which manifest as screen flickering or no display. The HDMI input on the adapter is a standard Type-A connector, and you need to provide a 5V power supply to the adapter board, typically 500 mA to 1 A, depending on the bridge chip. The LT8911B consumes about 200 mA at 3.3V, but the adapter board may include a voltage regulator that draws from the 5V input. The Rockchip board can also supply 3.3V power to the MIPI interface, but it is safer to use an external supply for the adapter to avoid overloading the SoC’s internal LDO.
Another critical detail is the I2C interface for the MIPI DSI configuration. The Rockchip board uses I2C to communicate with the MIPI DSI panel’s touch controller or backlight driver, but for the HDMI-to-MIPI adapter, the I2C bus is used to read the EDID from the bridge chip’s internal ROM. The adapter board typically has an I2C address of 0x3B or 0x3C for the LT8911B, and the Rockchip’s kernel driver must be configured to probe this address. On the RK3399, the I2C bus for MIPI DSI is usually I2C4 or I2C6, depending on the board layout. In the device tree, you need to set the rockchip,dsi node to include the bridge chip as a child node, with the compatible string set to "lontium,lt8911b" or "ite,it66121". The driver will then handle the EDID reading and MIPI DSI timing configuration. If the EDID is not read correctly, the HDMI source will not output a signal, and you will see a black screen. You can check the kernel log with dmesg | grep lt8911 to see if the bridge chip is detected. If not, check the I2C bus voltage—the adapter board typically uses 3.3V I2C, but some Rockchip boards use 1.8V, so you may need a level shifter.
Software Configuration in Device Tree and Kernel
The Rockchip board uses a Linux kernel with the DRM (Direct Rendering Manager) subsystem, and the MIPI DSI controller is handled by the dw-mipi-dsi driver (DesignWare MIPI DSI host controller) or the rockchip-dsi driver. The device tree must define the MIPI DSI node with the correct pinmux, clock references, and panel or bridge node. For the HDMI-to-MIPI adapter, you do not need a panel node because the bridge chip acts as a virtual panel. Instead, you define the bridge chip as a child of the MIPI DSI node, with the ports property to connect the MIPI output to the bridge input. A typical device tree snippet for the RK3399 with an LT8911B looks like this:
&dsi0 {
status = "okay";
rockchip,panel = <<8911b>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <<8911b_out>;
};
};
};
};
<8911b: lt8911b@3b {
compatible = "lontium,lt8911b";
reg = <0x3b>;
pinctrl-names = "default";
pinctrl-0 = <<8911b_rst>, <<8911b_int>;
reset-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
interrupt-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>;
dsi-lanes = <4>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lt8911b_in: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
Notice the dsi-lanes = <4> property, which tells the driver to use all four lanes. The reset GPIO is important—the LT8911B requires a low pulse of at least 10 ms to initialize. If the reset is not properly handled, the bridge chip may not respond over I2C. The interrupt GPIO is optional but can be used for hot-plug detection (HPD) from the HDMI source. The HDMI HPD signal is typically connected to a GPIO on the Rockchip board, and you can configure the kernel to detect when an HDMI cable is plugged in. On the adapter board, the HPD is usually pulled high by default, but some boards require an external pull-up resistor. The interrupt-gpios property in the device tree allows the driver to trigger a display hot-plug event, which can be handled by the userspace display manager. In practice, many users skip the HPD and just set the display to always on, but for proper HDMI hot-plug support, you need to wire the HPD pin to a GPIO that can generate an interrupt.
Once the device tree is compiled and flashed, the kernel will probe the bridge chip during boot. You can verify the detection by checking /sys/class/drm/ for a new connector, typically named card0-DSI-1. The resolution will be read from the EDID, and the DRM subsystem will set the mode accordingly. If the resolution is not what you expect, you can force a mode by setting the video=DSI-1:1920x1080@60 kernel parameter in the bootargs. The Rockchip’s display controller (VOP) must be configured to output to the MIPI DSI port. On the RK3399, the VOPB (Video Output Processor B) is typically used for MIPI DSI, while VOPL is used for HDMI. In the device tree, you set the vopb node to have a port connected to the MIPI DSI node. If you have dual displays, you can use VOPB for MIPI and VOPL for HDMI simultaneously, but that requires careful memory bandwidth management. The RK3399 has a total display bandwidth of 4.8 Gbps, so two 1080p@60Hz displays consume about 3.0 Gbps, leaving headroom for GPU rendering.
Practical Testing and Troubleshooting
When you first power on the system, the HDMI source (e.g., a laptop or a Raspberry Pi) should recognize the adapter as a monitor. If the screen remains black, the first thing to check is the power LED on the adapter board. If it is off, measure the 5V input voltage—it should be within 4.75V to 5.25V. The LT8911B has a built-in 1.2V LDO, so if the input voltage is too low, the chip may not initialize. Next, check the MIPI DSI clock using an oscilloscope if available. The clock lane should show a differential signal with a frequency of around 500 MHz to 1.0 GHz. If the clock is missing, the bridge chip may not be receiving the HDMI signal. Use a multimeter to measure the HDMI TMDS lines—each differential pair should have a DC bias of about 2.5V. If the HDMI source is not outputting, check the EDID. You can read the EDID from the adapter using the i2cdump command on the Rockchip board: i2cdump -y 4 0x3b (assuming I2C bus 4). The first 128 bytes should contain the standard EDID structure. If the dump returns all zeros, the bridge chip is not responding, which points to a hardware issue. Common causes are incorrect I2C address, missing pull-up resistors on the I2C lines, or a faulty bridge chip. The adapter board from DisplayModule uses a 0x3B address, but some clones use 0x3C, so you may need to adjust the device tree accordingly.
Another common issue is the MIPI DSI lane polarity. Some Rockchip boards have inverted lane assignments, meaning D0+ and D0- are swapped, or the clock lane polarity is inverted. The LT8911B has a register to invert the lane polarity, but the kernel driver may not expose this. In that case, you can try swapping the differential pairs manually by using a custom FPC cable. The adapter board typically has a 30-pin connector with a standard pinout: pin 1 is GND, pin 2 is D0+, pin 3 is D0-, and so on. The Rockchip board’s pinout may differ, so always check the schematic. For the RK3399 Firefly, the MIPI DSI connector is a 30-pin FPC with the following pinout: pin 1 is GND, pin 2 is D0+, pin 3 is D0-, pin 4 is GND, pin 5 is D1+, pin 6 is D1-, etc. The clock lane is on pins 13 and 14. If the adapter board uses a different order, you need to use a custom cable or a breakout board. The maximum cable length for MIPI DSI at 1.0 Gbps is about 15 cm, but with a good quality shielded cable, you can push it to 20 cm. Beyond that, signal integrity degrades, and you may see bit errors. The adapter board’s datasheet typically specifies the maximum cable length, so follow that.
For performance tuning, you can adjust the MIPI DSI clock frequency in the device tree by setting the clock-frequency property in the dsi0 node. The default is usually 500 MHz, but for 1080p@60Hz, you can lower it to 400 MHz to reduce power consumption. However, if the clock is too low, the bridge chip may not have enough bandwidth, resulting in pixel corruption. The LT8911B has a register to set the MIPI clock multiplier, and the driver can be modified to set this. On the RK3399, the MIPI DSI controller’s PLL is derived from the SoC’s 24 MHz crystal, so the clock frequency must be a multiple of 24 MHz. Common values are 480 MHz, 500 MHz, 528 MHz, and 600 MHz. The higher the clock, the more margin for error, but also higher power consumption. The adapter board’s datasheet recommends a MIPI clock of 500 MHz for 1080p@60Hz, which gives a data rate of 1.0 Gbps per lane. To verify the actual clock, you can read the bridge chip’s registers via I2C: i2cget -y 4 0x3b 0x0A